In a 3D chip stack, failures can occur in any multi-bit interconnect structure between chips. A typical solution to this problem is to provide spare interconnect channels that can be used to replace faulty channels as needed. Multiplexers and demultiplexers can be used to steer signals from a faulty channel to one of the spare channels. The number of spare channels, however, is typically pre-determined and thus inflexible. Furthermore, in 3D chip stacks connected using through silicon vias (TSVs), spare TSVs consume precious silicon “real estate” and routing resources.
In the figures, like reference numerals refer to the same figure elements.